Technology · Semiconductors
Fab Utilisation and Gross Margin
Depreciation is fixed, so a few points of utilisation move gross margin sharply. TSMC billing utilisation and Intel margin decline as worked cases.
Selborne Research · Semiconductors coverage: 9 guides, 6 company profiles, a primer and Excel model
Educational analysis. This guide is not investment advice or a recommendation to buy or sell any security, and it is not personalised.
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Fixed Depreciation Makes Utilisation a Margin Lever
A wafer fab’s depreciation schedule does not care how many wafers ran this quarter. When utilisation falls, revenue per fab falls while that depreciation stays. Gross margin therefore moves more than a variable-cost business would predict from the same volume change. A few points of loading can be the difference between a normal year and a trough year on the income statement.
Two filings make the mechanism concrete: TSMC while it still published billing utilisation, and Intel through a multi-year margin decline against heavy plant spend.
TSMC: Billing Utilisation and Gross Margin
TSMC’s FY2020 20-F carries the last published billing-utilisation series. Gross margins for the same years come from the 20-Fs.
| Fiscal year | Billing utilisation | Gross margin |
|---|---|---|
| 2016 | 92% | 50.1% |
| 2017 | 91% | 50.6% |
| 2018 | 87% | 48.3% |
| 2019 | 81% | 46.0% |
| 2020 | 94% | 53.1% |
Utilisation slipped from 92% to 81% between FY2016 and FY2019 while gross margin moved from 50.1% to 46.0%. The rebound to 94% utilisation in FY2020 came with 53.1% gross margin. Later filings stop publishing utilisation, so FY2021-FY2025 need a different read.
For FY2025, TSMC shipped 15.0M twelve-inch-equivalent wafers against capacity that exceeded 17M. That implies utilisation under 90%. Gross margin was 59.9%, up from 46.0% in FY2019, with chips at 7nm and below at 74% of wafer revenue. Mix and utilisation both matter; the fixed-cost lever is why under-loading still hurts even when the node mix is favourable.
Intel: Margin Compression Against a Large Fab Base
| Item | Figure | Fiscal year |
|---|---|---|
| Gross margin | 62.3% | FY2017 |
| Gross margin | 32.7% | FY2024 |
| Gross margin | 34.8% | FY2025 |
| Revenue | $79.0B | FY2021 |
| Revenue | $52.9B | FY2025 |
| Gross capex | $17.7B (33.4% of revenue) | FY2025 |
| Foundry operating loss | $10.3B on $17.8B revenue | FY2025 |
Intel’s gross margin roughly halved from FY2017 to the mid-2020s while revenue fell from the FY2021 level. The company continued to spend heavily on plant (gross capex 33.4% of FY2025 revenue; 27.7% on cash-flow additions). The foundry arm lost $10.3B in FY2025, on revenue that was mostly internal.
That is the IDM version of the same fixed-cost story TSMC’s utilisation series shows in a cleaner foundry form. Business-model definitions keep those cases from being compared as if they shared one cost structure.
How to Use Utilisation in Analysis
- Separate variable wafer costs from depreciation and other fixed fab costs.
- When utilisation is not disclosed, use shipments against stated capacity as a bound (as with TSMC FY2025).
- Do not treat a peak-utilisation margin as the mid-cycle rate; see peak versus mid-cycle margins.
- Tie the plant spend that created the depreciation base to capital intensity and the two-year lag from spend to capacity.
Fabless designers feel utilisation indirectly through wafer price and supply, not through their own depreciation line. Foundries and IDMs feel it directly. Knowing which model you are in decides whether utilisation is a footnote or the whole margin story.
Utilisation turns fixed fab costs into gross margin; the primer links wafer loading to margin in the foundry and integrated-maker models.
- 17 sections, from the business models and the industry cycle to capital intensity, memory, inventory, equipment orders, stock pay and a reverse DCF
- 44 pages
- a chip designer, a foundry, a memory maker and an equipment maker, all fictional
- 4 worked valuations
- listed chip companies on filed margins, capital intensity, inventory days and stock pay, each with its fiscal year
- 6-company screen
The Excel model is the primer's through-cycle DCF live across 13 sheets: a chip designer, a foundry, a memory maker and an equipment maker, all fictional, plus a column for a company of your own in any of five business-model modes. Each mode turns the industry cycle into revenue its own way: units and selling prices, capacity times utilisation times revenue per wafer, bit demand against bit supply, orders and installed-base services, or wafer starts for a materials supplier. Depreciation sits in cost of goods for fab owners, capacity arrives two years after the capex that pays for it, and the terminal value is struck on mid-cycle cash flow. A reverse DCF reads the margin and the growth a price requires, and the sensitivity grids re-run the model in every cell.
See what's in the Semiconductors Sector Primer →£25 PDF · £59 with the Excel model · £159 for all three Technology industries
Frequently Asked Questions
- Why does fab utilisation move gross margin so much?
- Depreciation and other fab fixed costs do not fall when wafers fall. Each lost wafer still carries its share of that fixed cost, so gross margin drops faster than revenue when utilisation slips.
- What utilisation has TSMC disclosed?
- TSMC published billing utilisation for FY2016 to FY2020: 92%, 91%, 87%, 81% and 94%. Gross margins in those years were 50.1%, 50.6%, 48.3%, 46.0% and 53.1%. Later 20-Fs do not publish the utilisation series.
- How loaded was TSMC in FY2025?
- TSMC shipped 15.0M twelve-inch-equivalent wafers against capacity that exceeded 17M, which implies utilisation under 90%. Gross margin that year was 59.9%.
- How does Intel illustrate under-utilisation?
- Intel gross margin fell from 62.3% in FY2017 to 34.8% in FY2025 while revenue fell from $79.0B in FY2021 to $52.9B in FY2025. The foundry segment lost $10.3B on $17.8B of mostly internal revenue in FY2025 against heavy plant spend.
Read next
Capital Intensity in Semiconductors
Capex to revenue sets what a chipmaker must earn. Spend reaches capacity about two years later; TSMC and Intel are the worked cases.
Fabless vs Foundry vs IDM vs OSAT
Four chip business models defined by who owns which assets, with margin and capex profiles from Nvidia, TSMC and Intel filings.
Peak vs Mid-Cycle Margins for Chip Companies
A terminal year at peak margin overstates value. Filed margin swings and a worked mid-cycle example on a fictional chip company.
See it applied
These company profiles apply the concepts from this guide to real public companies.