Technology · Semiconductors
Capital Intensity in Semiconductors
Capex to revenue sets what a chipmaker must earn. Spend reaches capacity about two years later; TSMC and Intel are the worked cases.
Selborne Research · Semiconductors coverage: 9 guides, 6 company profiles, a primer and Excel model
Educational analysis. This guide is not investment advice or a recommendation to buy or sell any security, and it is not personalised.
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Capex to Revenue Sets the Earnings Bar
A chipmaker that spends a third of sales on plant must earn a return on that plant after depreciation, or free cash flow stays thin even when gross margin looks fine. A fabless designer that spends a few percent of sales on equipment faces a different bar: its capital intensity sits at the foundry, paid through wafer price. Capital intensity is therefore a business-model fact before it is a year-specific forecast.
Spend also arrives late: capex reaches capacity about two years later. Near-term utilisation and margin still depend on fabs already built; today’s cheques show up in the wafer counts of the year after next.
Two Worked Cases: TSMC and Intel
| Company | Fiscal year | Capex measure | Capex % of revenue | Other filed facts |
|---|---|---|---|---|
| TSMC | FY2025 | Capex / revenue | 33.4% | Gross margin 59.9%; 15.0M wafers shipped against capacity over 17M |
| Intel | FY2025 | Cash-flow additions to PP&E | 27.7% | Gross margin 34.8%; operating margin -4.2% |
| Intel | FY2025 | Gross capex | 33.4% | $17.7B, of which $6.5B met by partners and incentives (net 21.2% of revenue) |
| Intel Foundry | FY2025 | Segment | $17.8B revenue, $10.3B operating loss (mostly internal) |
TSMC is the pure foundry load: customers bring designs; TSMC brings the plant. Capex was 33.4% of FY2025 revenue. Shipments of 15.0M twelve-inch-equivalent wafers against capacity above 17M imply utilisation under 90% even in a strong year, so the depreciation base is sized for more wafers than shipped.
Intel is the integrated-maker case with a funding twist. Gross capex matched TSMC’s 33.4% ratio, but $6.5B of the $17.7B was met by partners and government incentives, so net cash plant spend was 21.2% of revenue. Cash-flow additions alone were 27.7%. The foundry segment lost $10.3B on $17.8B of revenue, almost all internal: the capital programme and the under-loaded plant show up together.
The peer ladder across six filers is in capex to revenue by chip company.
Why the Two-Year Lag Matters in a Model
If year-1 free cash flow subtracts growth capex that will not produce wafers until year 3, and year-3 revenue assumes capacity that was never funded, the path is inconsistent. Schedule wafer additions by year of spend, delay their arrival by two years, and charge maintenance capex separately from growth. Depreciation then follows the PP&E roll-forward rather than a flat percentage that ignores the lag.
Utilisation and gross margin is the other half of the same fixed-cost story: once the plant is built, a few points of loading move margin sharply because depreciation does not flex.
Business Model Changes the Intensity
| Model | Who owns the fab | Typical capex posture in this set |
|---|---|---|
| Fabless | Foundry / OSAT | Low own-capex (Nvidia 2.8% of FY2026 revenue) |
| Foundry | Foundry | High (TSMC 33.4% of FY2025 revenue) |
| IDM | IDM | High when building (Intel, Texas Instruments) |
| Equipment | Chipmaker customers | Low own-capex (ASML 4.8% of FY2025 revenue); cycle shows in backlog |
Fabless versus foundry versus IDM versus OSAT defines the asset maps. The wafer fab equipment cycle is where the industry’s collective capex appears as tool orders rather than as one chipmaker’s ratio.
Capital intensity does not say whether a year was good. It says how much of each revenue dollar must go back into steel and tools before owners see free cash flow. Mid-cycle averages of that ratio belong in the terminal year next to mid-cycle margin.
Capital intensity and the two-year lag to capacity shape free cash flow; the primer reinvests at mid-cycle rates in the multi-period chip model.
- 17 sections, from the business models and the industry cycle to capital intensity, memory, inventory, equipment orders, stock pay and a reverse DCF
- 44 pages
- a chip designer, a foundry, a memory maker and an equipment maker, all fictional
- 4 worked valuations
- listed chip companies on filed margins, capital intensity, inventory days and stock pay, each with its fiscal year
- 6-company screen
The Excel model is the primer's through-cycle DCF live across 13 sheets: a chip designer, a foundry, a memory maker and an equipment maker, all fictional, plus a column for a company of your own in any of five business-model modes. Each mode turns the industry cycle into revenue its own way: units and selling prices, capacity times utilisation times revenue per wafer, bit demand against bit supply, orders and installed-base services, or wafer starts for a materials supplier. Depreciation sits in cost of goods for fab owners, capacity arrives two years after the capex that pays for it, and the terminal value is struck on mid-cycle cash flow. A reverse DCF reads the margin and the growth a price requires, and the sensitivity grids re-run the model in every cell.
See what's in the Semiconductors Sector Primer →£25 PDF · £59 with the Excel model · £159 for all three Technology industries
Frequently Asked Questions
- What is capital intensity in semiconductors?
- Capex divided by revenue, preferably stated gross of partner and government funding when those amounts are disclosed. It measures how much cash the business must reinvest to keep or grow capacity.
- How long until capex becomes capacity?
- Spend reaches capacity about two years later. Wafers funded in year 0 arrive as available capacity in year 2, so near-term utilisation still rides on plant already paid for.
- How capital intensive is a leading-edge foundry?
- TSMC capex was 33.4% of FY2025 revenue. That is the plant load of building and upgrading leading-edge capacity for customers who do not own fabs.
- How should Intel capex be read?
- FY2025 cash-flow additions to property, plant and equipment were 27.7% of revenue. Gross capex was $17.7B, or 33.4% of revenue, of which $6.5B was met by partners and government incentives. The foundry arm lost $10.3B on $17.8B of mostly internal revenue the same year.
Read next
Capex to Revenue by Chip Company
Ranked capex as a share of revenue for six chip filers. Business model sets the order from foundry and IDM down to fabless and equipment.
Fabless vs Foundry vs IDM vs OSAT
Four chip business models defined by who owns which assets, with margin and capex profiles from Nvidia, TSMC and Intel filings.
Fab Utilisation and Gross Margin
Depreciation is fixed, so a few points of utilisation move gross margin sharply. TSMC billing utilisation and Intel margin decline as worked cases.
The Wafer Fab Equipment Cycle
Equipment spend follows chipmaker capex, so it lags and leads the chip cycle. SEMI history and ASML backlog, bookings and service share.
See it applied
These company profiles apply the concepts from this guide to real public companies.