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Technology · Semiconductors

The Memory Pricing Cycle

DRAM and NAND are priced on bit supply against bit demand, so margins swing furthest. Micron filings show the trough and the peak.

Selborne Research · Semiconductors coverage: 9 guides, 6 company profiles, a primer and Excel model

Educational analysis. This guide is not investment advice or a recommendation to buy or sell any security, and it is not personalised.

On this page
  1. Memory Is a Commodity Priced on Bits
  2. Micron Across One Cycle
  3. Cost Per Bit Falls; Price Still Swings
  4. Mid-Cycle Is Not Optional in Memory
  5. What to Take From the Filings

Memory Is a Commodity Priced on Bits

DRAM and NAND sell on price per bit. When industry bit supply grows faster than bit demand, price falls; when demand outruns supply, price rises. Process technology also pushes cost per bit down over time, so producers are always racing a falling cost curve. A few points of oversupply can erase margin; a few points of shortage can push it to extremes.

That is why memory margins swing further than logic or analog in the same industry cycle. The worked case below is Micron Technology from its filings.

Micron Across One Cycle

ItemFigureFiscal year
Gross margin-9.1%FY2023
Gross margin80.7%FY2026
Revenue$133.2B (+256% year on year)FY2026
DRAM share of revenue75.6%FY2026
Capex / revenue23.1%FY2026
Days of inventory147FY2026
Fiscal calendar53 weeks (year ended 3 Sep 2026)FY2026

FY2023 was the trough on the income statement: a gross loss of $1.4B on $15.5B of revenue. FY2026 was the high point in these filings, with DRAM three-quarters of sales. The 53-week calendar means the +256% revenue growth includes an extra week; note it before treating the print as a pure 52-week run rate.

Inventory days at 147 in FY2026 sit mid-pack in the days ladder. The cycle shows up first in price and margin, not only in days.

Cost Per Bit Falls; Price Still Swings

Each new process node and stacking generation aims to deliver more bits from roughly the same wafer cost, so cost per bit trends down even when the industry is calm. Contract and spot prices do not follow that cost path smoothly. When supply additions land together, price per bit can fall faster than cost; when demand runs ahead of supply, price can rise while cost is still declining. Margin is the residual of that race.

A model that assumes a constant memory gross margin ignores the residual. One that lets price per bit move with the cumulative gap between bit demand growth and bit supply growth, subject to a floor so revenue cannot go absurdly negative in a deep glut, matches how the business behaves.

Mid-Cycle Is Not Optional in Memory

An 80.7% gross margin year is a real filing but a poor perpetuity: the same company printed -9.1% three fiscal years earlier. Peak versus mid-cycle margins states the method: average margin and capital intensity across one full cycle before you strike a terminal value.

The broader semiconductor inventory cycle still matters, because customers who over-order in a boom can destock memory too. Bit pricing and channel inventory can reinforce each other on the way down.

What to Take From the Filings

Use Micron FY2023 and FY2026 as bookends for how wide the income statement can move when bits are the product. Keep DRAM share and the 53-week note next to the FY2026 growth rate. For valuation work, put the mid-cycle average in the terminal year and let the explicit forecast carry the next swing, rather than pretending the peak is normal.

Semiconductors Sector Primer

Bit balance and cost-per-bit decline drive the memory model; the primer prices bits through the cycle and strikes the terminal at mid-cycle margin.

17 sections, from the business models and the industry cycle to capital intensity, memory, inventory, equipment orders, stock pay and a reverse DCF
44 pages
a chip designer, a foundry, a memory maker and an equipment maker, all fictional
4 worked valuations
listed chip companies on filed margins, capital intensity, inventory days and stock pay, each with its fiscal year
6-company screen

The Excel model is the primer's through-cycle DCF live across 13 sheets: a chip designer, a foundry, a memory maker and an equipment maker, all fictional, plus a column for a company of your own in any of five business-model modes. Each mode turns the industry cycle into revenue its own way: units and selling prices, capacity times utilisation times revenue per wafer, bit demand against bit supply, orders and installed-base services, or wafer starts for a materials supplier. Depreciation sits in cost of goods for fab owners, capacity arrives two years after the capex that pays for it, and the terminal value is struck on mid-cycle cash flow. A reverse DCF reads the margin and the growth a price requires, and the sensitivity grids re-run the model in every cell.

See what's in the Semiconductors Sector Primer →

£25 PDF · £59 with the Excel model · £159 for all three Technology industries

Frequently Asked Questions

What drives DRAM and NAND prices?
Bit supply against bit demand. When bits shipped grow faster than bits demanded, price per bit falls; when demand outruns supply, price rises. Cost per bit also trends down as process technology improves, so the price path is a race between cost reduction and the supply-demand balance.
How far can memory gross margins swing?
Micron reported a -9.1% gross margin in FY2023 and an 80.7% gross margin in FY2026. That span is the widest filed swing in the semiconductor peer set used on these pages.
Why does Micron use a 53-week fiscal year?
Micron FY2026 ended 3 September 2026 and contained 53 weeks. Comparisons to a 52-week year need that calendar note before growth rates are read as pure run-rate change.
Why must memory valuations use mid-cycle margins?
A terminal year struck at an 80% gross margin treats a shortage peak as perpetual. Averaging margin and capital intensity across one full cycle stops a peak setting the long-run rate.

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